1. Technical Field
The disclosed embodiments relate to level shifting circuits, and more particularly relate to high speed level shifting circuits that exhibit both low duty cycle distortion and high supply voltage margin.
2. Background Information
Digital logic circuits can be powered from different supply voltages. In one example, an integrated circuit includes a first digital logic block that operates with a first supply voltage as well as a second digital logic block that operates with a second supply voltage. If a digital signal is to pass form one logic block to the other, the digital levels of the signal must be shifted. A circuit referred to as a level shifter is sometimes used to perform this level shifting function.
FIG. 1 (Prior Art) is a circuit diagram of a conventional level shifter 1. The label VDDL designates a first supply voltage (for example, 1.2 volts) whereas the label VDDH designates a second supply voltage (for example, 1.8 volts). If a digital input signal IN on input node 2 transitions from a digital low logic level (for example, ground potential or approximately ground potential) to a digital high logic level (for example, VDDL or approximately VDDL), then inverter 3 causes the signal on node 4 to transition low, and inverter 5 causes the signal on node 6 to transition high (to VDDL), and inverter 7 causes the signal on node 8 to transition low (to ground potential). The signal on node 6 transitioning to VDDL causes thick-gate insulator N-channel transistor 9 to turn on. The signal on node 8 transitioning to ground potential causes thick-gate insulator N-channel transistor 10 to turn off. Transistor 9 being turned on pulls the voltage on node 11 down to ground potential, and therefore causes thick-gate insulator P-channel transistor 12 to turn on. Transistor 10 being turned off allows conductive transistor 12 to pull the voltage on node 13 up toward the second supply voltage VDDH. The high voltage on node 13 causes thick-gate insulator P-channel transistor 14 to be turned off. It is therefore seen that the low-to-high transition from ground potential to VDDL on input node 2 is shifted into a low-to-high transition from ground potential to VDDH on node 13. The digital signal on node 13 passes through two inverters 15 and 16 in this example and is then buffered by yet another buffer 17 before the signal on node 18 is used by the second digital logic block that operates with the second supply voltage VDDH.
The level shifting circuit of FIG. 1 works well in many applications, but as signal speeds increase, the level shifting circuit is seen to introduce an undesirable amount of duty cycle distortion skew into the signal. A low-to-high signal transition has a first propagation delay (TPD_LH) through the circuit whereas a high-to-low signal transition has a second propagation delay (TDP_HL) through the circuit. The high-to-low propagation delay time is significantly affected by how fast N-channel transistor 10 can pull the voltage on node 13 down and switch the signal on node 13. The low-to-high propagation delay time is significantly affected by how fast P-channel transistor 12 can pull the voltage on node 13 up and switch the signal on node 13. The sizes of transistors 10 and 12 can be adjusted so that there is little or no skew at a certain set of operating voltage, process and temperature conditions. Unfortunately, as the operating voltages, process and temperature of the circuit vary, the low-to-high and high-to-low propagation delay times differ from one another.
In one example, a level shifter circuit is desired that will conduct 400 MHz digital signals. If, for example, the signal being level shifted is a data signal being communicated from a transmitter circuit to a receiver circuit synchronously with a clock signal, and if the time that the signal arrives at the receiver varies, then the rate at which the clock signal can be clocked is reduced. The clock signal cannot transition to clock data into the receiver until the data has been received at the receiver. In the 400 MHz signal application, a circuit specification requires that if a square wave is supplied as an input to the level shifting circuit, then the level shifted signal that is output from the circuit must have a duty cycle of no less than thirty percent and must have a duty cycle of no more than seventy percent over all permutations of voltage, process and temperature corners. Unfortunately, the circuit of FIG. 1 can have a duty cycle distortion greater than this.
FIG. 2 is a waveform diagram that illustrates how a 50/50 duty cycle 400 MHz input signal IN that is input to the circuit of FIG. 1 is level shifted into an output signal OUT that has an 80/20 duty cycle. This is more duty cycle distortion than is allowed by the circuit specification. An improved circuit is desired.